Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4073
Title: Data path allocation with interconnection optimization in high-level synthesis
Authors: Zhu, Hongwei.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2001
Abstract: In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.
URI: http://hdl.handle.net/10356/4073
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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