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|Title:||Digital baseband for IEEE 802.15.4 transmitter||Authors:||Zheng, Mei Hong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2010||Abstract:||IEEE 802.15.4 is a new standard uniquely designed for low date rate, low power consumption and low cost wireless networking and offers device level wireless connectivity. It has a wide range of applications in personal short range wireless communication devices. Nowadays, it is also widely used in biomedical devices for signal processing. This Project focuses on the Offset Quadrature Phase Shift Keying (OQPSK) modulator inside the IEEE 802.15.4 transceiver with 2.4 GHz operation. It contains two major parts: construction of OQPSK modulator using Matlab Simulink and the design of half-sine pulse-shaping filter circuit for the OQPSK modulator. The OQPSK modulator constructed with Matlab Simulink are simulated with the input bit frequency of 10 Hz and carrier frequency of 20 Hz. The result waveform verifies that the OQPSK modulated signal is sinusoidal and has constant amplitude, phase. However, the frequency varies. The half-sine pulse-shaping filter is one of the major components in the OQPSK modulator. It helps reduce the signal bandwidth to save the frequency spectrum. The first design of the half-sine pulse shaping filter is analogous to the digital Finite Impulse Response (FIR) filter. The design contains multipliers and a shift register and hence is more complex. The second half-sine filter with a simplified circuit comes out. It contains a 7-bit output signal and has a sampling frequency that is four times the input data bit rate. After synthesizing, a simple RTL schematic is derived. It contains a counter, a logic gate ANDB2B, a D-flip-flop and a ROM. The functionality of the circuit is then verified using Xilinx Spartan-3E FPGA demo board and HP 1660E Logic Analyzer. For future development, the output of the circuit could be further transformed into continues time signal by connecting into a Digital to Analog Converter (DAC).||URI:||http://hdl.handle.net/10356/40735||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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Updated on Nov 30, 2020
Updated on Nov 30, 2020
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