Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4073
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dc.contributor.authorZhu, Hongwei.en_US
dc.date.accessioned2008-09-17T09:43:50Z-
dc.date.available2008-09-17T09:43:50Z-
dc.date.copyright2001en_US
dc.date.issued2001-
dc.identifier.urihttp://hdl.handle.net/10356/4073-
dc.description.abstractIn this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits-
dc.titleData path allocation with interconnection optimization in high-level synthesisen_US
dc.typeThesisen_US
dc.contributor.supervisorJong, Ching Chuenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US
item.grantfulltextrestricted-
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