Design of a CMOS class AB op amp with a constant input transconductance

Abstract

Power consumption has become a major concern for every analog device manufacturing company. As the demand for compact and portable devices has become more and more nowadays, success in reducing power consumption while being able to scale down means a big success in business. Being one of the most fundamental building blocks of analog system, it is a challenge to design an operational amplifier in small size and yet remains in good operation under low voltage. This report presents detailed steps and considerations to successfully design a low voltage class AB output operational amplifier. Besides capable of operating under low voltage of 1.2V or even in worst case of 1V, the op-amp has a total input transconductance variation of 14.9% over the entire common-mode input voltage. To obtain this, a simple structure consist of four transistors is inserted in the first stage as the biasing circuit. The second stage of the op-amp is a class AB output, whose control circuit is shifted into the summing circuit for lower noise and offset of the amplifier. The completed op-amp has a DC gain of more than 80dB with excellent phase margin of 60o and a gain bandwidth of 8.371MHz for supply voltage of 1.2V. In addition, the circuit possesses good common-mode rejection ratio of more than 65dB and a power supply rejection ratio index of more than 54dB. Other than that, quiescient current is well controlled and gives a value of 94.07 µA. Cadence custom IC Design Tools (Virtuoso Front to Back Design Environment, version 5.10.41.500.4.67) based on 0.18 CSM CMOS N-well process is the design tool required to complete the project.