Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/40789
Title: Design of the low-voltage CMOS analog multiplier
Authors: Chong, Hauo Wah.
Keywords: DRNTU::Engineering
Issue Date: 2010
Abstract: Analog Multiplier is an electronic device that performs linear multiplication of two continual input signals. It found its extensive uses in analog signal processing. In this report, different architectures of multipliers reported are discussed. Advantages and disadvantages of each topology were studied before the final design was proposed. The multiplier proposed is operating in saturation region, which follows the concept of Type V multiplier discussed in literature review. The structure of this final design is made up with four different parts: single-ended to differential conversion, impedance conversion, trans-conductance multiplier and lastly the modified cascade current mirror to deliver the output signal. These different parts of the circuit serve to improve the performances of the multiplier. Design of current sources and output buffer are described in this report as well. 0.18um process technology was adopted. Simulation in software cadence was conducted to verify the performance of the proposed structure. The proposed structure is operational with 1.3 V supply voltage and maximum ±0.2 V input signals. THD performance is less than 5% at 100MHz. It can drive an output load of at least 10kΩ in parallel with 150pF. Operating temperature is between -45oC and 85oC, typically at room temperature, which is 27oC.
URI: http://hdl.handle.net/10356/40789
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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