Low power flip-flop circuits for high-performance systems

Abstract

The increasing demand of portable applications motivates the research on low power and high speed circuits. The tighter timing constraint as well as the low power requirement has made the timing elements such as latches and flip-flop critical to the performance of a digital system.

In this project, studies were done on State-Of-The art of flip-flop designs particularly on double edge-triggered flip-flop for low power and high performance system. Four conditional techniques were discovered and have implemented two of those techniques in the proposed design.

A new low power flip-flop for high performance system is proposed. The proposed design demonstrated a gain in power consumption as activity rate of the flip-flop, α, decreases. At α = 1.0, α = 0.5, α = 0.25 and α = 0, the proposed design achieve power saving of 8%, 15%, 16% and 37%, respectively compare to other State-Of-The art dual edge-triggered flip-flops. On top of this, the proposed design is able to operate at a supply voltage of 1.22 V which is at least 13% lower compare to other designs. Furthermore, the proposed circuit is able to operate at a maximum clocking frequency of 1.48 GHz. Besides, the Monte Carlo analysis shows that the proposed design has high immunity to process variations with 87.29% of this design will have its tCQ fall within ±10% of the mean value.

System level simulation was done to verify the credibility of designs. All designs studied were configured as a component in synchronous binary counter with size ranging from 4 bits to 32 bits. The proposed design has achieved a reduction of 27% in power consumption and 33% improvement in Power-Delay-Product (PDP).