Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/40846
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dc.contributor.authorKwantono, Hendra.-
dc.date.accessioned2010-06-22T08:39:08Z-
dc.date.available2010-06-22T08:39:08Z-
dc.date.copyright2010en_US
dc.date.issued2010-
dc.identifier.urihttp://hdl.handle.net/10356/40846-
dc.description.abstractIn this project two linear regulators based on a new topology is designed. This topology allows a linear regulator to have a fast settling time and Power-Supply Ripple Rejection (PSRR) of 40dB up to 1MHz while consuming current less than 26μA. The two regulators, High Dropout Regulator (HDO) and Low Dropout Regulator (LDO), provide an output of 1.8V using 1.2V reference from 3.3V supply and 2V supply while capable of driving maximum load of 1A and 100mA load respectively. A low-voltage low-power high-PSRR bandgap reference circuit has also been designed to provide the 1.2V voltage reference with temperature coefficient of 52ppm/⁰C to the regulator. The bandgap reference circuit can operate at supply voltage as low as 2V while consuming current not more than 1μA.en_US
dc.format.extent84 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Power electronicsen_US
dc.titleAn LDO with high drive and fast responseen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorChan Pak Kwongen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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