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https://hdl.handle.net/10356/40846
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DC Field | Value | Language |
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dc.contributor.author | Kwantono, Hendra. | - |
dc.date.accessioned | 2010-06-22T08:39:08Z | - |
dc.date.available | 2010-06-22T08:39:08Z | - |
dc.date.copyright | 2010 | en_US |
dc.date.issued | 2010 | - |
dc.identifier.uri | http://hdl.handle.net/10356/40846 | - |
dc.description.abstract | In this project two linear regulators based on a new topology is designed. This topology allows a linear regulator to have a fast settling time and Power-Supply Ripple Rejection (PSRR) of 40dB up to 1MHz while consuming current less than 26μA. The two regulators, High Dropout Regulator (HDO) and Low Dropout Regulator (LDO), provide an output of 1.8V using 1.2V reference from 3.3V supply and 2V supply while capable of driving maximum load of 1A and 100mA load respectively. A low-voltage low-power high-PSRR bandgap reference circuit has also been designed to provide the 1.2V voltage reference with temperature coefficient of 52ppm/⁰C to the regulator. The bandgap reference circuit can operate at supply voltage as low as 2V while consuming current not more than 1μA. | en_US |
dc.format.extent | 84 p. | en_US |
dc.language.iso | en | en_US |
dc.rights | Nanyang Technological University | - |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Power electronics | en_US |
dc.title | An LDO with high drive and fast response | en_US |
dc.type | Final Year Project (FYP) | en_US |
dc.contributor.supervisor | Chan Pak Kwong | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Bachelor of Engineering | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | restricted | - |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
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EB2017-091.pdf Restricted Access | 3.45 MB | Adobe PDF | View/Open |
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