Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4142
Title: Modeling of PCI with SystemVerilog
Authors: Chithambaram Shaalini.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2005
Abstract: Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification.
URI: http://hdl.handle.net/10356/4142
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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