Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4214
Title: High performance architecture for move generation in computer chess : an FPGA based implementation
Authors: De Silva, C. R.
Keywords: DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Issue Date: 1999
Abstract: This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are then implemented in hardware, enabling them to operate in parallel contributing to the overall system throughput. Two novel concepts that contribute mostly to high performance architecture are introduced in this thesis.
URI: http://hdl.handle.net/10356/4214
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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