Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4214
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dc.contributor.authorDe Silva, C. R.en_US
dc.date.accessioned2008-09-17T09:46:52Z-
dc.date.available2008-09-17T09:46:52Z-
dc.date.copyright1999en_US
dc.date.issued1999-
dc.identifier.urihttp://hdl.handle.net/10356/4214-
dc.description.abstractThis thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are then implemented in hardware, enabling them to operate in parallel contributing to the overall system throughput. Two novel concepts that contribute mostly to high performance architecture are introduced in this thesis.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence-
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems-
dc.titleHigh performance architecture for move generation in computer chess : an FPGA based implementationen_US
dc.typeThesisen_US
dc.contributor.supervisorAmarasinghe, S. K.en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US
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