Power sensitive techniques for high productivity embedded systems

Abstract

Energy consumption is a major issue in modern day embedded applications. With the cache memory consuming about 50% of the total energy expended in these systems, predictor based filter cache hierarchies have been introduced to reduce the energy consumption of the instruction cache by leveraging on a smaller cache to store the many tiny loops inherent in embedded applications. In light of this, there exists a need to identify the optimal filter cache and L1 cache size for an embedded application. In this work, we introduce a framework for systematic tuning of predictor based instruction cache hierarchies without the need for exhaustive memory hierarchy simulation. Simulations based on programs from the MiBench benchmark suite shows that the proposed framework is capable of identifying optimal cache sizes due to its sensitivity to spatial and temporal locality. The exploration using the proposed techniques is also notably faster when compared to exhaustive design space exploration for identifying optimal cache sizes as it relies on only a one-time simulation. Instruction set customization is fast becoming a preferred approach to meet the performance requirements of embedded applications. It is of interest to examine the implications on the overall energy-delay product reduction when a combined optimization through cache hierarchy tuning and instruction set customization is performed.