Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4251
Title: Investigation of design techniques to reduce glitches for low power
Authors: Foo, Chee Yin.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Issue Date: 2003
Abstract: This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.
URI: http://hdl.handle.net/10356/4251
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
EEE-THESES_304.pdf
  Restricted Access
5.04 MBAdobe PDFView/Open

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.