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https://hdl.handle.net/10356/4251| Title: | Investigation of design techniques to reduce glitches for low power | Authors: | Foo, Chee Yin. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Power electronics | Issue Date: | 2003 | Abstract: | This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits. | URI: | http://hdl.handle.net/10356/4251 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Theses |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| EEE-THESES_304.pdf Restricted Access | 5.04 MB | Adobe PDF | View/Open |
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