Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/42749
Title: Digital system design with FPGA using verilog HDL
Authors: Cho, Shao Ying.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Issue Date: 2010
Abstract: In this final year project (Digital system design with FPGA using Verilog HDL) CORDIC is selected as the digital system to be designed. CORDIC is a simple and yet efficient algorithm for computing the hyperbolic and trigonometric functions, without the need of complex hardware multipliers and dividers, thus reducing the speed of the computation and the cost of the hardware tremendously. In the project, 2 versions of CORDIC, namely a 16-bit and a 20-bit design, were designed and implemented. The report details the design, implementation and hardware testing. In this project, the CORDIC is designed to handle all the functions, including the cosine, sine, tangent, hyperbolic cosine, hyperbolic sine, hyperbolic tangent, arctangent, hyperbolic arctangent, vector, rotation, square root, exponential, division and nature logarithm. The designs are coded in Verilog HDL. Their functionalities are simulated with Xilinx ISE. After the functionalities are verified, the designs are synthesized and implemented. They are also tested on a Xilinx Spartan 3E FPGA board. The detailed designs of the modules are described and the design considerations are discussed. Xilinx LogiCORETM IP CORDIC designs are also generated and compared with the designs in this project. The comparison results in terms of result accuracy, hardware resource utilization and computation speed are presented.
URI: http://hdl.handle.net/10356/42749
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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