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|Title:||Development of a software program for module allocation and interconnection optimisation in high-level synthesis of VLSI systems||Authors:||Goo, Chong Kiat.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems||Issue Date:||2002||Abstract:||The objective of this project is to search for a new algorithm to solve the module allocation and interconnection problems. Current algorithms and techniques were studied and a new technique was developed and implemented.||URI:||http://hdl.handle.net/10356/4307||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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