Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/4315| Title: | Low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications | Authors: | Gu, Jiangmin | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | Issue Date: | 2005 | Source: | Gu, J. (2005). Low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications. Master’s thesis, Nanyang Technological University, Singapore. | Abstract: | We present in this thesis several algorithms and designs, and their IC implementation of low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications. The design methodologies span from circuit level, architecture level to algorithm level. | URI: | https://hdl.handle.net/10356/4315 | DOI: | 10.32657/10356/4315 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Theses |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| EEE-THESES_362.pdf | 17.54 MB | Adobe PDF |  View/Open |
Page view(s) 20
744
Updated on May 7, 2025
Download(s) 5
689
Updated on May 7, 2025
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.