Please use this identifier to cite or link to this item:
|Title:||65 nm BEOL electro-copper plating gap fill capability study||Authors:||Deng, Fangxin||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics||Issue Date:||2011||Source:||Deng, F. (2011). 65 nm BEOL electro-copper plating gap fill capability study. Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||The objectives of this project include reducing Cu void defects, prolonging metal electromigration (EM) lifetime and improving wafer yield. As a result of the project, the Ta/TaN/Ta tri-layer barrier in the advanced direct contact via (ADCV) structures, via bottom removal and 3-step Cu seed for dual damascene (DD) Cu metallization were studied and implemented successfully in 65 nm technology-node products. The comparative study of the samples with the tri-layer and bi-layer barriers shows that the samples with tri-layer barrier have lower defective die percentage. Downstream EM test reveals that the samples with tri-layer barrier have downstream EM lifetime three times more than those of the samples with bi-layer barrier. ADCV structures with three different via bottom removals were comparatively investigated. Median removal in the ADCV split is found to result in the lowest defective die percentage. Meanwhile, the highest activation energy and the longest downstream EM lifetime are achieved with this process. However, it exhibits median via contact resistance as the tradeoff to the longer EM lifetime.||URI:||https://hdl.handle.net/10356/43218||DOI:||10.32657/10356/43218||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.