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|Title:||Electrical characterization of IC packages||Authors:||Guruprasad B. G.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging||Issue Date:||2003||Abstract:||In this project, a PBGA package 3D lumped element model is developed and its parasitics are extracted using a FEM based solver. The package data is validated with a standard measurement procedure developed by JEDEC. This simulation methodology can be extended to other critical signals and packages, and the parasitics can be extracted.||URI:||http://hdl.handle.net/10356/4325||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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