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|Title:||System analysis and design of dual-mode digitally controlled dc-dc converters||Authors:||Han, Dong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Power electronics||Issue Date:||2009||Abstract:||Recently, the dual-mode digitally controlled DC-DC converters - (hereafter named “dual-mode converters” for brevity) have received an increasing focus from designers because of the benefits of high power efficiency over wide loading range, flexible proportional-integral-derivative (PID) control law, and convenient interface with micro-controller. The overall control loop of the dual-mode converter is a mixed-signal negative feedback loop which includes the analog-to-digital converter (ADC), PID controller, digital dither, pulse-width modulator (PWM), and pulse-frequency modulator (PFM). Involving such mixed-signal control loop makes the system analysis and design of the dual-mode converter complex and challenging. How to predict the system performance and optimize the system design are the challenges raised to the designers. This dissertation develops a complete specification-oriented system level model for systematically analyzing and optimizing of the dual-mode converters. To the best of our knowledge, this system model is the first model which provides the minimum ripple dither code ,  with dynamic resolution and supports hybrid-mode simulation (co-simulation of the system level mode and transistor level circuit). Based on this model, an optimized system design of the dual-mode converter with high power efficiency, wide loading range and small output ripple is proposed and validated. A novel charge pump counter based ADC is implemented and validated simulation in Chartered 0.18µm CMOS process with improved quantization size (10mV) and reduced power consumption (7.5µW). This work has been titled as “a low power analog to digital interface for digitally controlled DC-DC converter” and published in the proceeding of the 23rd international technical conference on circuits, systems computers and communications (ITS-CSCC) . A low power (200nW) ring oscillator is also designed to provide the system clock. With designed ADC and ring oscillator, the hybrid-mode system simulation is performed. The simulation results meet the specifications and further validate the system design of the dual-mode converter.||URI:||http://hdl.handle.net/10356/43530||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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