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Title: Design of high performance continuous time sigma delta ADC
Authors: Zhang, Fan
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2011
Source: Zhang, F. (2011). Design of high performance continuous time sigma delta ADC. Master’s thesis, Nanyang Technological University, Singapore.
Abstract: ΣΔ technique has always been the popular choice for designing high resolution data converters due to the advantage of oversampling and noise shaping. In recent years, continuous time implementation of ΣΔ modulator is attracting more and more research attention for its superior potential to realize low power low voltage and/or high speed design. CT ΣΔ modulator relaxes amplifier‘s unity gain bandwidth requirements which greatly improves its achievable conversion speed. It also has the advantage of implicit anti-aliasing feature. In this research, various design trade-offs and implementation issues have been introduced and discussed. Special focus has been put on the issue of clock jitter which is considered to be the major obstacle for CT ΣΔ modulator to be widely implemented. In this research, a special pulse shaping technique which is called fixed length return-to-zero method was proposed. Simulation shows that it almost achieves the best performance any pulse shaping method can achieve. It not only greatly improves CT modulator‘s jitter performance, but also exerts very little adverse effects such as increased power consumption, circuit overhead, and increased loop delay. For the purposed of verifying various design concepts developed in this research, a 4th order 1-bit prototype modulator integrated in 0.18 μm CMOS technology has been developed. Simulation shows it is able to achieve 85 dB SNDR for 25 kHz input signal range. And the FOM it achieves is 0.22pJ/conversion. The total chip occupies an area of 1.725mm2.
DOI: 10.32657/10356/43538
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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