Electromigration study of through silicon via (TSV)
Tan, Yeow Chong
Date of Issue2010
School of Electrical and Electronic Engineering
In the continuous drive for smaller chips (Moore’s Law) and heterogeneous semiconductor applications, traditional processing and packaging technologies may not be able to support this trend. 3-D IC can offer a greater packing density in the same footprint as 2-D miniaturizing is reaching its physical limit. Through Silicon Via (TSV) is one of the most promising and key enabling technology for 3-D IC. However, TSV technology puts high demands on the process module and integration. This brings about reliability issues ranging from process related such as void-free filling and scalloping of sidewalls to thermo-mechanical stress/strain induced defects during both operation and manufacturing. Numerous thermo-mechanical analyses have been reported and reliability test experiments are carried out. In contrast with the extensive study of thermo-mechanical analyses on TSV, electromigration (EM) study of TSV is rarely reported. Recently, it is found that the driving forces for EM is not solely the current density, but temperature gradient and its resulting thermo-mechanical stress are as significant as the current density in affecting the EM of an interconnect. In view of the high thermo-mechanical stress in the TSV as has been well studied, it is worthwhile to look at the EM performance of TSV as well. This work is to study the EM performance of TSV in Silicon interposer application. Finite Element (FE) modeling and simulation employing ANSYS is carried out. Established models successfully applied in the area of EM in ULSI interconnects where Atomic Flux Divergence (AFD) is used as a merit of EM performance will be adopted.
DRNTU::Engineering::Electrical and electronic engineering::Semiconductors