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Title: Low power continuous-time sigma delta modulator
Authors: Teh, Li Lian.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2011
Abstract: The rapidly growing market for portable electronic systems such as wireless communication devices or battery powered electronic devices increases the demand for low-voltage and low-power circuits and building blocks. Reducing the power dissipation in integrated circuits is required to minimize the recharging cycles or to extend the battery lifetime as much as possible. This work presents the realization of a continuous-time (CT) sigma-delta (Σ?) analog-to-digital converter (ADC) that can achieve 87dB SNRP, 85dB SNDR and 90dB DR with 3.2MS/s output data rate at 1.5V supply using the 1.8V/0.18μm CMOS process. A fully differential 4th-order single-loop, single-bit modulator is employed in this work to provide sufficient noise shaping for the quantization noise and internal sampling error. Several system and circuit design techniques have been utilized which aim to achieve high resolution, low power consumption CT Σ? ADC. Cascaded integrators with feedfoward summation are chosen to implement the loop filter since it is more power efficient. Return-to-zero (RZ) feedback digital-to-analog converters (DACs) is employed to reduce the inter-symbol interference (ISI) problems which would otherwise degrade the modulator linearity and hence the maximum achievable signal-to-noise ratio (SNR). Single-loop architecture is used to relax the matching requirement of the loop filter which is suitable for a 14-bit high resolution ADC. By combining different techniques to address various design challenges, the modulator consumes only 207OW with 3.2MHz sampling rate and the entire die occupies 1.725mm2. die chip area including pads.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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