Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/43988
Title: FPGA-aware custom instructions for reconfigurable instruction set processors
Authors: Lam, Siew Kei
Keywords: DRNTU::Engineering::Computer science and engineering::Computer systems organization
Issue Date: 2011
Source: Lam, S. K. (2011). FPGA-aware custom instructions for reconfigurable instruction set processors. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: It is evident that future embedded systems will continue to demand a higher degree of customization and design flexibility without compromising the Time-To-Market (TTM), and lower Non Recurring Engineering (NRE) costs. In this thesis, techniques for the automatic generation of profitable custom instructions for FPGA based Reconfigurable Instruction Set Processors (RISPs) have been proposed. A detailed literature review was undertaken to establish the shortcomings in the existing work on RISPs. In particular, challenges in the selection, hardware estimation, area-time optimization and runtime reconfiguration of custom instructions for FPGA based RISPs have been established. A method for the selection of custom instructions has been proposed and compared with the existing ones reported in the literature. The proposed technique based on Largest-Fit-First (LFF) has been shown to yield large custom instructions that are capable of representing a number of frequently executed ones. It was shown that the outputs generated using LFF can be further refined by considering the overlapping templates that were previously ignored. Performance evaluations show that the proposed technique outperforms the existing methods by up to 32%. Moreover, the proposed selection process can be realized in the order of milliseconds.Techniques for the rapid estimation of critical path delays and area measures of custom instructions implemented on LUT based FPGAs have been devised. The proposed high level estimation technique relies on partitioning the custom instructions into a set of basic clusters to facilitate the systematic mapping onto FPGA logic blocks.
URI: https://hdl.handle.net/10356/43988
DOI: 10.32657/10356/43988
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Theses

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