dc.contributor.authorLam, Siew Kei
dc.date.accessioned2011-05-18T04:31:28Z
dc.date.accessioned2017-07-23T08:29:15Z
dc.date.available2011-05-18T04:31:28Z
dc.date.available2017-07-23T08:29:15Z
dc.date.copyright2011en_US
dc.date.issued2011
dc.identifier.citationLam, S. K. (2011). FPGA-aware custom instructions for reconfigurable instruction set processors. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/43988
dc.description.abstractIt is evident that future embedded systems will continue to demand a higher degree of customization and design flexibility without compromising the Time-To-Market (TTM), and lower Non Recurring Engineering (NRE) costs. In this thesis, techniques for the automatic generation of profitable custom instructions for FPGA based Reconfigurable Instruction Set Processors (RISPs) have been proposed. A detailed literature review was undertaken to establish the shortcomings in the existing work on RISPs. In particular, challenges in the selection, hardware estimation, area-time optimization and runtime reconfiguration of custom instructions for FPGA based RISPs have been established. A method for the selection of custom instructions has been proposed and compared with the existing ones reported in the literature. The proposed technique based on Largest-Fit-First (LFF) has been shown to yield large custom instructions that are capable of representing a number of frequently executed ones. It was shown that the outputs generated using LFF can be further refined by considering the overlapping templates that were previously ignored. Performance evaluations show that the proposed technique outperforms the existing methods by up to 32%. Moreover, the proposed selection process can be realized in the order of milliseconds.Techniques for the rapid estimation of critical path delays and area measures of custom instructions implemented on LUT based FPGAs have been devised. The proposed high level estimation technique relies on partitioning the custom instructions into a set of basic clusters to facilitate the systematic mapping onto FPGA logic blocks.en_US
dc.format.extent235 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computer systems organizationen_US
dc.titleFPGA-aware custom instructions for reconfigurable instruction set processorsen_US
dc.typeThesis
dc.contributor.researchCentre for High Performance Embedded Systemsen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorThambipillai Srikanthan (SCE)en_US
dc.description.degreeDOCTOR OF PHILOSOPHY (SCE)en_US


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