Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4467
Title: Efficient architecture for MPEG-4 binary shape decoder
Authors: Jagannatharaja Thinakaran, J. T.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2002
Abstract: The objective of this project is to design an efficient architecture for MPEG-4 binary shape decoder. The efficiency if the architecture is investigated in terms of speed and area. Power minimization is also taken into consideration.
URI: http://hdl.handle.net/10356/4467
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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