Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4545
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dc.contributor.authorLai, Chung Wohen_US
dc.date.accessioned2008-09-17T09:53:54Z
dc.date.available2008-09-17T09:53:54Z
dc.date.copyright2002en_US
dc.date.issued2002
dc.identifier.urihttp://hdl.handle.net/10356/4545
dc.description.abstractThis report explains the need for ultra shallow junctions for modern day CMOS devices, how spike anneal can help achieve this, reviews the important parameters if this process and how these parameters affect the performances of the CMOS transistors.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Microelectronics
dc.titleImpact of spike anneal on ultra shallow junction formationen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Microelectronics)en_US
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