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|Title:||Asynchronous-logic 8051 microcontroller and circuits : dynamic voltage control||Authors:||Chang, Kok Leong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2011||Abstract:||This thesis pertains to digital-logic design methodologies/approaches that yield robust error-free energy-efficient digital-logic circuits/systems for full-range Dynamic Voltage Control (DVC), including at wide operation and variation spaces. The first part pertains to an investigation and design (including realization thereof) of a synchronous-logic 8051 microcontroller core and a proposed asynchronous-logic 8051 microcontroller core for full-range DVC and at wide operation and variation spaces. A salient aspect of said first part is the embodiment of standard library cells for sake of equitable benchmarking with the synchronous-logic counterpart – such cells are not optimized for asynchronous-logic Quasi-Delay-Insensitive realization. Hence, the second part pertains to the proposal of an asynchronous-logic Quasi-Delay-Insensitive realization approach for full-range DVC and at wide operation and variation spaces. The investigations and design proposals presented in this thesis are useful as they provide digital-logic circuit/system IC designers useful insight into the basis of selecting the appropriate digital-logic design philosophies/approaches that yield robust error-free operation for full-range DVC and at wide operation and variation spaces.||URI:||http://hdl.handle.net/10356/45502||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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