Error-tolerant multiplier for high speed application
Khaing, Yin Kyaw
Date of Issue2011
School of Electrical and Electronic Engineering
With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems. Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing. The aim of this project is to develop a new type of multiplier to fulfill this need. In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed. The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy. To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work. The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM). As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits