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https://hdl.handle.net/10356/45661
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DC Field | Value | Language |
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dc.contributor.author | Khaing, Yin Kyaw | en |
dc.date.accessioned | 2011-06-16T01:37:27Z | en |
dc.date.available | 2011-06-16T01:37:27Z | en |
dc.date.copyright | 2011 | en |
dc.date.issued | 2011 | en |
dc.identifier.citation | Khaing, Y. K. (2011). Error-tolerant multiplier for high speed application. Master’s thesis, Nanyang Technological University, Singapore. | en |
dc.identifier.uri | https://hdl.handle.net/10356/45661 | en |
dc.description.abstract | With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems. Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing. The aim of this project is to develop a new type of multiplier to fulfill this need. In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed. The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy. To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work. The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM). As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM. | en |
dc.format.extent | 107 p. | en |
dc.language.iso | en | en |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | en |
dc.title | Error-tolerant multiplier for high speed application | en |
dc.type | Thesis | en |
dc.contributor.supervisor | Yeo Kiat Seng | en |
dc.contributor.supervisor | Goh Wang Ling | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en |
dc.description.degree | MASTER OF ENGINEERING (EEE) | en |
dc.identifier.doi | 10.32657/10356/45661 | en |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | EEE Theses |
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eG0502446C_Updated.pdf | 1.4 MB | Adobe PDF | View/Open |
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