High resolution time-to-digital converter

Abstract

This paper presents the design of a closed-loop time difference amplifier (TDA) with a novel self-calibration technique. The proposed design takes use of two cross-coupled NAND gates operating in metastable region to amplifier input time difference of two signals. The design is based on the published topology in section 2.3. By adding new design blocks and modifying the original structure of [1], the gain and calibration speed of the TDA is doubled, and the maximum input signal frequency is improved by one quarter. The gain of the TDA is stabilized, with an input of 0.05~1 Td (one buffer delay), over a large PVT variation: from SS to FF process corner, +/-10% supply voltage, and -40 to 80 0C. The proposed TDA is designed using IBM 0.13 um CMOS process technology with power supply voltage of 1.4 V. the simulation results show that the gain deviation of the TDA is well controlled within 1.26% under all circumstances, with regard to the gain in typical PVT condition. The whole circuit consumes 1.32 mW average powers with an input signal of 50 MHz.