Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/45908
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dc.contributor.authorWong, Wee Kiat.-
dc.date.accessioned2011-06-23T07:12:40Z-
dc.date.available2011-06-23T07:12:40Z-
dc.date.copyright2011en_US
dc.date.issued2011-
dc.identifier.urihttp://hdl.handle.net/10356/45908-
dc.description.abstractThis project report describes the design of an integrated circuit to implement a logarithmic converter based on the Combet’s 4-region (C4) logarithmic conversion algorithm from the front end design (HDL coding of the design specifications) to the back end (layout). The Combet’s 4-region (C4) logarithmic conversion algorithm involves piecewise linear approximation of the mantissa, dividing the mantissa curve into 4 regions. The computation of the approximation involves simple shifting and counting operations that can be easily implemented by hardware. The design is to be described in Verilog HDL at RTL level in the Mentor Graphics Modelsim environment. Modelsim is also used for functional simulation, back annotated simulation and verification. Gate level logic synthesis will then be carried out using Synopsys Design Compiler. Various constraints are provided to optimize the area and timing of the design. The gate level netlist generated by the Design Compiler is to be used in the placement and routing of the design.en_US
dc.format.extent107 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleDesign and implementation of a digital integrated circuit for logarithmic conversion (C4)en_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorJong Ching Chuenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
item.grantfulltextrestricted-
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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