Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4598
Title: Design of a low-voltage CMOS analogue multiplier
Authors: Leow, Hee Boon.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2005
Abstract: The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing of more than lOmV. Its' main application is primarily used for voice signal processing.
URI: http://hdl.handle.net/10356/4598
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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