Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46011
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dc.contributor.authorLiew, Tien Wei.
dc.date.accessioned2011-06-27T07:48:52Z
dc.date.available2011-06-27T07:48:52Z
dc.date.copyright2011en_US
dc.date.issued2011
dc.identifier.urihttp://hdl.handle.net/10356/46011
dc.description.abstractTechnology scaling has caused many issues for analog design. The op-amp based pipelined ADC which using the charge transfer technique using high gain, high speed manner had become an issue when the scaling down of device size and supply voltage occur. This project study a comparator based pipelined ADC which uses a zero crossing detector circuit for special case comparator. By using the zero crossing detector circuit, this circuit claim to have high speed, low power and suitable to be used in a 0.18um technology with 1.8V power supply. This report include the result of simulation of the comparator based pipelined ADC using a zero crossing detector under cadence environment with CSM018IC technology.en_US
dc.format.extent51 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleLow-power comparator-based pipelined ADCen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorSiek Literen_US
dc.contributor.supervisorTiew Kei Teeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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