Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46198
Title: Design and analysis of class-E power amplifier
Authors: Khoo, Fatt Seng.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2011
Abstract: In this paper, based on the specification assigned, I have designed a low voltage Class-E Power Amplifier (PA) using the 0.18μm TSMC CMOS technology from BSIM3 model to achieve the following results: f = 5.8GHz, Pout = 13.003dBm, VDD = 1.8VDC, Bandwidth = 200MHz, Termination = 50Ω, Power Added Efficiency = 71.3%. The design of Class-E PA network contains the presence of parasitics and losses in the switch and shunt-capacitor. The transistor will provide an optimum PAE (power added efficiency). Lastly, the design is simulated and fine-tuning to it resonant to achieve the maximum power control capabilities.
URI: http://hdl.handle.net/10356/46198
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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FYP_Report-Fatt Seng.docx
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Design and Analysis of Class E Power Amplifier1.17 MBMicrosoft WordView/Open
Advance Design System-CEPA.zip
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Advance Design System528.32 kBView/Open

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