Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46228
Title: Design of low-voltage low-power nano-scale SRAMs
Authors: Do, Anh Tuan
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2010
Source: Do, A. T. (2010). Design of low-voltage low-power nano-scale SRAMs. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Static Random Access Memory (SRAM)- based cache is one of the most important components of state-of-the-art VLSI systems. It is responsible for increasing the speed of data flows, and hence the speed of the whole electronics system. SRAM is prevalently utilised in the design of modern microprocessors for bridging the widening divergence between the performances of the Central Processing Unit (CPU) and the Dynamic RAM (DRAM)-based memory.
URI: https://hdl.handle.net/10356/46228
DOI: 10.32657/10356/46228
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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