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|Title:||Ultra wideband amplifier and pulse synthesizer design||Authors:||Fang, Chao||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio||Issue Date:||2011||Source:||Chao, F. (2011). Ultra wideband amplifier and pulse synthesizer design. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The objective of this Ph.D. dissertation is to describe the design and implementation of two key components for ultra-wideband (UWB) wireless system. The first is a high gain and low noise amplifier (LNA) for the UWB receiver. The second is a novel distributed UWB pulse synthesizer for the UWB transmitter. First, the background knowledge on UWB wireless system is presented. Literature review on various broadband circuit techniques such as the reactively matched circuit technique, feedback circuit technique, lossy match circuit technique and distributed circuit technique are conducted. Various distributed amplifier topologies such as the cascode distributed amplifier, capacitively-coupled distributed amplifier and cascaded single-stage distributed amplifier are also discussed. Previous published UWB LNA and Federal Communications Commission (FCC) compliance UWB pulse generation circuits are reviewed and the gaps are identified which forms the author’s research work. Subsequently, a 3.1-10.6 GHz UWB two–stage low noise amplifier based on 0.15-μm pHEMT technology is presented. The size of the fabricated UWB LNA is 0.9 mm x 2.5 mm = 2.25 mm2. The first stage of the LNA was designed by employing a resistive shunt feedback topology together with 2 T sections low pass structure in order to match to a 50-ohm antenna. At the same time this topology will improve the noise performance compared to the distributed input stage. The second stage is implemented in common source configuration in order to achieve higher power gain compared to common gate configuration. Finally, resistive output matching network is used to drive an external 50-ohm antenna. Current sharing among the transistors of the two stages is employed to reduce power consumption. Frequency domain measurement results show that the 3.1-10.6 GHz 0.15-μm pHEMT MMIC amplifier has state of the art performance consuming only 12.9 mW of power.||URI:||https://hdl.handle.net/10356/46512||DOI:||10.32657/10356/46512||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Aug 3, 2021
Updated on Aug 3, 2021
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