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|Title:||ASIC implementation of a video decoder||Authors:||Dang Bao Duc||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2011||Abstract:||As digital signal processors have optimized instruction sets to manage the required operations so image and video codec is implemented mainly in software. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application Using ASIC/FPGA device to implement a codec increased processing speed due to the use of customized hardware. The JPEG algorithm was chosen for this project because it is ordinarily used in many multimedia applications, and is an important standard for video compression today. The JPEG includes many compression techniques such as variable length coding, discrete cosine transform, quantization…. Variable length coding (VLC) reduces data redundancy based on assigning short codeword to frequent symbols and long codeword to infrequent symbols. In the design of VLC decoder (VLD), the most important objective is to achieve high throughput. Many algorithms and architectures of VLD have been proposed. This project will be focus on Constant output rate decoder for VLD. The simulations of the model show that the design proposed in this thesis can meet the real time requirement for HD video decoding||URI:||http://hdl.handle.net/10356/46536||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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