Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46536
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dc.contributor.authorDang Bao Duc
dc.date.accessioned2011-12-15T03:41:24Z
dc.date.available2011-12-15T03:41:24Z
dc.date.copyright2011en_US
dc.date.issued2011
dc.identifier.urihttp://hdl.handle.net/10356/46536
dc.description.abstractAs digital signal processors have optimized instruction sets to manage the required operations so image and video codec is implemented mainly in software. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application Using ASIC/FPGA device to implement a codec increased processing speed due to the use of customized hardware. The JPEG algorithm was chosen for this project because it is ordinarily used in many multimedia applications, and is an important standard for video compression today. The JPEG includes many compression techniques such as variable length coding, discrete cosine transform, quantization…. Variable length coding (VLC) reduces data redundancy based on assigning short codeword to frequent symbols and long codeword to infrequent symbols. In the design of VLC decoder (VLD), the most important objective is to achieve high throughput. Many algorithms and architectures of VLD have been proposed. This project will be focus on Constant output rate decoder for VLD. The simulations of the model show that the design proposed in this thesis can meet the real time requirement for HD video decodingen_US
dc.format.extent70 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleASIC implementation of a video decoderen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorHo Duan Juaten_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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