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|Title:||Low-voltage low-power CMOS flip-flops||Authors:||Phyu, Myint Wai.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2009||Source:||Phyu, M. W. (2009). Low-voltage low-power CMOS flip-flops. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||As the clock frequency scales, the pipeline depth increases and the number of logic gates per stage decreases. The System-on-Chip (SoC) designs will therefore integrate tens of millions of transistors on one chip. But the packaging and cooling designs have only a limited ability to remove the excess heat produced by the systems. All these factors have resulted in power consumption to be considered as one of the main problems in achieving high performance designs. The energy consumption of the clocking sub-system that is composed of the clock distribution networks (buffers and wires) and clock storage elements (flip-flops and latches) is about 30% to 60% of the total system energy. For this clock system power, 90% is consumed by the flip-flops themselves and the last branches of the clock distribution network that drives the flip-flop directly. As clock frequency increases, the latency of the flip-flop will play an even greater role in the overall cycle time. As a result, it is essential to continue venturing into higher-end approaches and realizing more refined solutions to achieve low-voltage/lowpower design while sustaining high-speed performance and small-area consumption. In this thesis, several innovative flip-flop designs for low-voltage low-power environments used are described.||Description:||186 p.||URI:||http://hdl.handle.net/10356/46774||Rights:||Nanyang Technological University||metadata.item.grantfulltext:||restricted||metadata.item.fulltext:||With Fulltext|
|Appears in Collections:||EEE Theses|
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