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dc.contributor.authorRao Vinayak Sheeravantheen_US
dc.description92 p.en_US
dc.description.abstractComputational complexity is one of the major concerns in the design of video encoders, especially for low power devices with very limited Mega instructions per second (MIPS). Conventional block-matching algorithms (BMAs) reduces the computational complexity of motion estimation by sophisticatedly inspecting a subset of checking points, stops only once all those checking points are examined and does not consider available computation power. This results in frame drop and reduction in video quality when total computation power is exhausted. Our primary goal in this project is to maximize the coding efficiency for a given computation power. A novel computation-aware scheme is proposed, which first dynamically determines the target amount of computation power allocated to a frame, and then allocates this to each block in a computation-distortion-optimized manner. The proposed computation allocation scheme can be incorporated into the widely used BMA, such as diamond, three step search (TSS), new three step search, four-step search, and hexagonal, to develop their corresponding computation-aware BMAs versions. The simulation result shows that the proposed algorithm is simple yet effective compared to an existing computation allotment scheme for software based motion estimation.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Data::Coding and information theoryen_US
dc.titleComputation-ware block motion estimation for video codingen_US
dc.contributor.supervisorZhu Ceen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Signal Processing)en_US
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