Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46790
Title: Electrical modeling of through-silicon-via for 3D integrated circuits
Authors: Santhosh Onkaraiah.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2011
Abstract: Increased use of technology in day to day life for seamless activity and increased living comforts have been driving the Integrated Circuit (IC) industry to produce better hardware at cheaper and faster rate. Hence Ultra Large Scale Integration (ULSI) of ICs is accelerating to account for the need of high speed systems. Traditional scaling alone is believed to be insufficient to satisfy the interconnect performance going forward. Hence equivalent scaling using unconventional approaches would be necessary. As the scaling of integrated circuits to achieve faster, denser and smaller devices continues to drive the industry, we are at the juncture where many hurdles need to be addressed to continue on this remarkable journey of semiconductors. International Technology Roadmap for Semiconductors [ITRS] projects that the device delay is continuously scaling down but interconnect delays are increasing at a rapid rate for global and semi global interconnects
Description: 117 p.
URI: http://hdl.handle.net/10356/46790
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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