Algorithm and circuit design for conversion of binary numbers to signed power-of-two terms

Abstract

Improvements in VLSI technology have enabled digital filters to be used in an increasing number of application domains. In a full custom hardware implementation, the coefficient multiplier is the most expensive and the most important speed determining component. Consequently the primary concern in the design of filters for hardware implementation is to reduce the multiplier complexity. Many methods have been proposed to reduce the hardware complexity of digital filters. One of these methods is to approximate each coefficient value by a small number of signed power-of-two terms (SPT) as the number of SPT terms is proportional to the hardware complexity which is the aim of this thesis.