Please use this identifier to cite or link to this item:
Title: Test methods for gals processor
Authors: Ye Myat Thu.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2010
Abstract: As the feature size of the transistor gate reduces, the on-chip clock frequency can increase. The circuit design with conventional synchronous design method becomes a challenging task with regards to clock distribution and skew, especially at high clock frequencies. Furthermore, the power delivery and noise issues become more severe. A fully asynchronous design method could overcome these problems but suffers from significant overhead in terms of execution time and hardware. Moreover, the asynchronous design suffers the lack of design tools. The GALS based approach partitions the system into synchronous modules and uses a handshake protocol for communications. Hence, GALS uses a divide-and-conquer approach that significantly improves the design efficiency [12]. The synchronous modules are encapsulated in order to further reduce the complexity.
Description: 58 p.
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
6.07 MBAdobe PDFView/Open

Page view(s)

Updated on Oct 2, 2023


Updated on Oct 2, 2023

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.