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|Title:||Low jitter frequency multiplier||Authors:||Yin, Jee Khoi.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2010||Source:||Yin, J. K. (2010). Low jitter frequency multiplier. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||This thesis I explore the research in the area of low jitter frequency multipliers before proposing a novel new design for such a multiplier. The thesis begins with an analysis of the random and deterministic noise arising from conventional phaselocked loop (PLL) and delay-locked loop (DLL) based frequency multipliers. Although the DLL is a better candidate for use as a low jitter frequency multiplier, analysis shows that the jitter performance of the DLL can be jeopardized by the cascading structure of the delay cells. Thus, a new architectural form is proposed. In this design, the delay chain of the conventional DLL is replaced by a polyphase filter (PPF) to generate clock edges for frequency multiplication purposes. A fundamental jitter analysis shows that the random jitter performance of the proposed PPF frequency multiplier outperforms that of the conventional DLL. Because the clock edges generated by the PPF have a larger mismatch when compared to their DLL counterparts, an analog-based phase error calibration (PEC) circuit is proposed to reduce the phase error. In doing so, both the random and deterministic jitter can be minimized and a frequency multiplier with better jitter performance is achieved.||Description:||182 p.||URI:||http://hdl.handle.net/10356/46842||Rights:||Nanyang Technological University||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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