Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46842
Full metadata record
DC FieldValueLanguage
dc.contributor.authorYin, Jee Khoien
dc.date.accessioned2011-12-23T10:00:16Zen
dc.date.available2011-12-23T10:00:16Zen
dc.date.copyright2010en
dc.date.issued2010en
dc.identifier.citationYin, J. K. (2010). Low jitter frequency multiplier. Doctoral thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/46842en
dc.description182 p.en
dc.description.abstractThis thesis I explore the research in the area of low jitter frequency multipliers before proposing a novel new design for such a multiplier. The thesis begins with an analysis of the random and deterministic noise arising from conventional phaselocked loop (PLL) and delay-locked loop (DLL) based frequency multipliers. Although the DLL is a better candidate for use as a low jitter frequency multiplier, analysis shows that the jitter performance of the DLL can be jeopardized by the cascading structure of the delay cells. Thus, a new architectural form is proposed. In this design, the delay chain of the conventional DLL is replaced by a polyphase filter (PPF) to generate clock edges for frequency multiplication purposes. A fundamental jitter analysis shows that the random jitter performance of the proposed PPF frequency multiplier outperforms that of the conventional DLL. Because the clock edges generated by the PPF have a larger mismatch when compared to their DLL counterparts, an analog-based phase error calibration (PEC) circuit is proposed to reduce the phase error. In doing so, both the random and deterministic jitter can be minimized and a frequency multiplier with better jitter performance is achieved.en
dc.rightsNanyang Technological Universityen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleLow jitter frequency multiplieren
dc.typeThesisen
dc.contributor.supervisorChan Pak Kwongen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en
dc.identifier.doi10.32657/10356/46842en
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:EEE Theses
Files in This Item:
File Description SizeFormat 
EEE_THESES_184.pdf18.28 MBAdobe PDFThumbnail
View/Open

Page view(s) 50

364
Updated on Nov 26, 2021

Download(s) 10

357
Updated on Nov 26, 2021

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.