Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4685
Title: Advanced planarization techniques for deep sub-micron applications
Authors: Lim, Victor Seng Keong.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2001
Abstract: In this work, the evolution of step height, film thickness and unformity, on both the STI test structures and SDRAM structure throughout the CMP process were characterized in detailed. Comparision made among the newly proposed scheme and the conventional processes such as Direct Polish (DP) Scheme and the Reverse Mask (RT) Scheme were also presented.
URI: http://hdl.handle.net/10356/4685
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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