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Title: A low-phase-noise CMOS LC VCO for operation in the 3-4 GHz range
Authors: Suraj Kamath.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2011
Abstract: This project on LC VCO contributes part of a larger ongoing project on a PLL Based Frequency synthesizer generating five fixed output frequencies in the 1-2 GHz frequency range. The frequency synthesizer is an industrial project for defense applications and emphasizes low phase noise performance. The frequencies to be synthesized are 1.2, 1.6, 1.7, 1.8 and 1.9GHz. The emphasis of the PLL design is on low phase noise performance. The phase noise specification is -lOOdBc/Hz at 10 KHz, -HOdBc/Hz at lOOKHz and -120dBc/Hz at 1MHz. The equipment in use today utilizes uses a VCO implemented using discrete bipolar devices and high-Q off chip inductors. The PLL project explores the feasibility of a completely integrated CMOS implementation of this frequency synthesizer. Such a system-on-chip implementation is crucial to reducing the size and weight of the communication equipment and increasing its portability and reliability.
Description: 135 p.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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