Algorithms for synthesis and optimization of multiplierless FIR filters
Date of Issue2007
School of Electrical and Electronic Engineering
Centre for High Performance Embedded Systems
The use of transformations in high-level synthesis of Very Large Scale Integration (VLSI) circuits has led to the development of powerful optimization methods for many compute intensive digital signal processing problems. One such class of applications is digital filters which are modeled as a generic multiple constant multiplication (MCM) problem by decomposing the computational intensive multiplier in their implementation into shifters and simpler arithmetic operators. This thesis presents the study of synthesis and optimization of multiplierless finite impulse response (FIR) digital filters. In this research, work has been done to scrutinize the characteristics of Canonical Signed Digits (CSD) number system, and to investigate the feasibility of sharing crucial common subexpressions in filter synthesis algorithm and new and efficient algorithms for improving the logic complexity and logic depth of FIR filter implementation. The ultimate goal is to establish a set of technology independent design automation algorithms that allows a quick path to the application specific integrated circuit (ASIC) cores to meet stringent filtering specifications.
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Nanyang Technological University