Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/46983
Title: Constraint-based watermarking techniques for VLSI IP protection
Authors: Cui, Aijiao
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Issue Date: 2009
Source: Cui, A. (2009). Constraint-based watermarking techniques for VLSI IP protection. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: With the increase, in the popularity of reusable intellectual property (IP) cores for System-on-a-Chip (SoC), piracy is also on the rise in this new design area. The lure of getting a new product ahead of the competitor at a fraction of, or at no cost, is often too much a temptation to ignore, which results in an increasingly buoyant IP theft. To safeguard the IP owner against piracy and illegal redistribution of the IP cores, constraint-based watermarking has been used as a pivotal technology to protect the copyright of the very large scale integration (VLSI) IPs. In this thesis, a comprehensive framework of constraint-based watermarking techniques has been studied and explored at different design abstraction levels. The goal is to develop robust watermarking chemes and techniques for VLSI IP protection that can facilitate easy detection and tracking of IP misappropriation.
Description: 172 p.
URI: https://hdl.handle.net/10356/46983
DOI: 10.32657/10356/46983
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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