Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/47030
Title: FPGA implementation of product accumulate codes
Authors: Koh, Tiong Aik
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2009
Source: Koh, T. A. (2009). FPGA implementation of product accumulate codes. Master’s thesis, Nanyang Technological University, Singapore.
Abstract: Product accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec).
Description: 129 p.
URI: https://hdl.handle.net/10356/47030
DOI: 10.32657/10356/47030
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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