FPGA implementation of product accumulate codes
Koh, Tiong Aik
Date of Issue2009
School of Electrical and Electronic Engineering
Product accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec).
DRNTU::Engineering::Electrical and electronic engineering
Nanyang Technological University