Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/47030
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dc.contributor.authorKoh, Tiong Aiken
dc.date.accessioned2011-12-27T05:56:06Zen
dc.date.available2011-12-27T05:56:06Zen
dc.date.copyright2009en
dc.date.issued2009en
dc.identifier.citationKoh, T. A. (2009). FPGA implementation of product accumulate codes. Master’s thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/47030en
dc.description129 p.en
dc.description.abstractProduct accumulate (PA) codes are a class of low density parity check (LDPC)-like codes with a well defined structure, which allows flexible rate and length adaptation while maintaining good bit error rate (BER) performance. Compared to turbo codes, they provide similar performance but with significantly less decoding complexity and with a lower error floor. This thesis presents our study on the various design tradeoffs needed for the field programmable gate array (FPGA) implementation of PA codes and on the actual FPGA implementation of the PA type I encoder and decoder (codec).en
dc.rightsNanyang Technological Universityen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleFPGA implementation of product accumulate codesen
dc.typeThesisen
dc.contributor.supervisorGuan Yong Liangen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.degreeMASTER OF ENGINEERING (EEE)en
dc.identifier.doi10.32657/10356/47030en
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Appears in Collections:EEE Theses
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